AMD is looking to patent new techniques for switching between two different CPU architectures on-the-fly in a similar manner to the “big.Little” design ARM uses for its own processors. Given that we’ve already heard rumors that Intel’s Alder Lake will deploy a comparable configuration, it’s beginning to look like this could be a common feature between major CPU vendors going forward. Also, while we’ve referred to “big.Little,” that’s technically an ARM-specific invention. The more generic term would likely be hybrid computing or heterogeneous computing. While the latter term has typically been used for CPU + GPU compute models, two CPUs with two different levels of ISA support on the same silicon would also qualify as a heterogeneous compute model.
One of the implications of this shift is that there’s an advantage to using dedicated CPU cores for specific functions. When Intel first announced it would enter the smartphone industry, the company claimed its DVFS approach would be as effective as big.Little. Intel wound up leaving the smartphone market, at least in part due to Qualcomm’s own antitrust abuses, and we never really saw a full range of solutions from either company that could be compared effectively.
The patent, available here, was first picked up by @Underfox3, who notes it is still in the adjustment process. It describes a method of using ISA features rather than voltage or frequency to move between the CPU cores. Linus Torvalds recently complained about AVX-512, partly because support for the ISA is so fragmented across Intel’s product lines. AMD’s idea for how to switch between ISA’s isn’t necessarily tied to AVX-512 or any other SIMD instruction set, but the idea of using a difference like this as a method of waking CPU cores is a clever one.
This is a patent, not a roadmap, and I want to stress that AMD has not articulated any actual plan to build this kind of chip. Companies regularly file for patents on technologies they do not bring to market and they maintain patent war chests to protect themselves against predatory behavior by patent trolls.
AMD would have three options for a new low-power core. It could build a low-power Ryzen cluster tuned for high efficiency and low clocks with much smaller caches, it could design a new high-efficiency core from scratch, or it could go back and improve Jaguar. AMD’s Jaguar is outdated now, but back in 2013 the CPU core won accolades compared with Intel’s Atom for offering substantially better CPU and GPU performance. A modernized Jaguar core would be substantially smaller and more power-efficient.
Making desktop CPUs more efficient by leveraging different types of onboard CPUs might help improve efficiency in several ways. It might allow for faster overall performance by distributing little cores in a different slice of silicon, allowing them to cooperate with big cores on some multi-threaded workloads without contributing to hot spot formation on the big-core chiplet. It could allow Intel and AMD to create new CPUs with a better balance between efficiency and performance. Intel’s Lakefield is a good example of what this kind of effort might look like. Finally, it might be possible to further optimize the silicon and design rules used for both options by building them on physically separate chiplets.
While I have no idea if AMD will actually build a hybrid processor, these are the sort of concepts companies are exploring to continue improving performance. As lithography nodes offer fewer improvements with every generation, the industry has turned its attention to packaging and interconnect performance. There’s an increased emphasis on developing the right tool for the right job rather than relying on the improvements of historical Moore’s law scaling to do the heavy lifting. These trends shift so gradually it can be difficult to see happening in the moment, but it wouldn’t surprise me to see CPU designs from both Intel and AMD reflect these focus shifts over the next few years.
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